Design-Reuse1d
Creonic Introduces Doppler Channel IP Core
Kaiserslautern, Germany, January 14, 2025 - Creonic GmbH, the leading provider of cutting-edge communications IP cores, ...
Design-Reuse6d
Qualitas Semiconductor and Verisilicon signed a licensing agreement for 4nm PCIe 6.0 PHY IP
QUALITAS SEMICONDUCTOR, a leading provider of high-speed interconnect solutions, has announced the supply of its 4nm PCIe 6.0 ...
Design-Reuse6d
What is JESD204C? A quick glance at the standard
The JESD204C standard enables establishing high-speed serial links between a Controller and ADC and DAC converters. JESD204C ...
Design-Reuse14h
InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
The next-generation UCIe physical layer IP, based on TSMC's N4 process, is expected to finalize its design later this year, ...
Design-Reuse2d
E21 High-performance, full-featured Embedded processor
The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected ...
Design-Reuse2d
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB slave interface and so can be driven by software or ...
Design-Reuse2d
high performance duel channel audio DAC
ITC26MDAC is a high performance DAC based on FPGA.It can be used for digital audio devices such as HIFI. Its data input is based on 8X times over sampling (Interpolation) and 16X/32X CIC digital ...
Design-Reuse2d
Single Port SRAM Compiler GlobalFoundries 55LPx Ultra-high density, low power, up to 320K bits
Proven Single Port SRAM compiler for GF55 LPx - Memory optimized for ultra high density and high speed with compiler range up to 320K bits ...
Design-Reuse2d
Full-Speed USB 2.0 PHY
The MUSBFPHY IP PHY from Mentor Graphics?is an on-chip transceiver for USB On-The-Go (OTG) that complies with both the USB standard for Full-Speed functions and the OTG supplement to the USB 2.0 ...
Design-Reuse2d
Serial NOR Flash Memory Model
Serial NOR Flash Memory Model provides an smart way to verify the Serial NOR Flash component of a SOC or a ASIC. The SmartDV s Serial NOR Flash memory model is fully compliant with standard Serial NOR ...
Design-Reuse2d
Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation. Racyics® dense 9T logic standard cells libraries and ...
Design-Reuse2d
SPI (Serial Peripheral Interface) Verification IP
SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI basic ...