How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.

AI-driven automation, tighter design-test collaboration, and evolving BiST techniques are redefining DFT strategies.

A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...

Dr. Patrick Heissler, CEO, SCRONA AG, discusses the company’s recently unveiled 128-nozzle electrohydrodynamic (EHD) ...

Net sales of $1.026 billion, down 11.8% sequentially and down 41.9% from the year ago quarter. Our updated guidance provided on December 2, 2024 was net sales of $1.025 billion.On a GAAP basis: gross ...

Ceva has recently unveiled the Ceva-Waves Links200 multi-protocol platform IP with support for Bluetooth LE High Data ...

Last year computer maker Framework announced plans to release a RISC-V Mainboard for its 13 inch laptops. Then the company launched an early access program in November. And now the DeepComputing ...

Last year computer maker Framework announced plans to release a RISC-V Mainboard for its 13 inch laptops. Then the company launched an early access program in November. And now the DeepComputing ...

STMicroelectronics and HighTec EDV-Systeme collaborate for safer software-defined vehicles Where safety meets safety: ST's Stellar MCUs certified to the highest level of risk management, ISO 26262 ASI ...

Been some time since Leo did a 'Leo Says' - but he put together this article discussing Intel Nodes and details on what has ...

Leo is currently in ISRAEL with Intel - much of which is under strict NDA. While he was at Intel's canteen however he managed ...

The RISC-V microcontroller NXP EdgeLock A30 is an "authenticator" that stores digital information and protects it from unauthorized modification. Among other things, the A30 is intended for use as ...