EDN4h
Why RISC-V is a viable option for safety-critical applications
How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.
Analytics India Magazine2d
IIT Madras, ISRO Successfully Developed and Booted Indigenous Microprocessor for Space Applications
The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and ...
IIT Madras & ISRO Develop Indigenous Microprocessor For Space Applications
New Delhi: Indian Institute of Technology (IIT) Madras and ISRO have developed an indigenous microprocessor for space ...
LOWRISC C.I.C.: Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-Ibex
Collaboration milestone addresses key pain points of typical design verification, the open silicon ecosystem organisation, ...
Semiconductor Engineering2d
Maximizing Energy Efficiency in Subthreshold RISC-V Cores (NTNU)
A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...
EDN4h
u-blox grows Bluetooth LE module portfolio
New variants in the u-blox Nora-B2 Bluetooth LE 6.0 module family integrate Nordic’s entire nRF54L series of ultra-low power ...
The Manila Times4d
Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-Ibex
(GLOBE NEWSWIRE) -- lowRISC C.I.C., the open silicon ecosystem organisation, today announced the addition of formal ...
IIT Madras develops indigenous Shakti semiconductor chip for ISRO
IIT Madras develops indigenous Shakti semiconductor chip for ISRO, marking a milestone in Make in India efforts.
IIT-Madras and ISRO collaborate to develop aerospace-quality IRIS Chip
IIT Madras and ISRO developed and tested the SHAKTI-based IRIS chip for aerospace applications, promoting indigenized ...