How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.

The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and ...

IIT Madras develops indigenous Shakti semiconductor chip for ISRO, marking a milestone in Make in India efforts.

IIT Madras and ISRO develop the SHAKTI microprocessor, an indigenous chip for space applications, enhancing command, control, ...

IIT Madras and ISRO developed and tested the SHAKTI-based IRIS chip for aerospace applications, promoting indigenized ...

The IRIS (Indigenous RISC-V Controller for Space Applications) chip was developed by IIT Madras in collaboration with ISRO’s ...

A joint effort with ISRO Inertial Systems Unit, Thiruvananthapuram, the chip was manufactured at Semiconductor Laboratory ...

A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...

Collaboration milestone addresses key pain points of typical design verification, the open silicon ecosystem organisation, ...

(GLOBE NEWSWIRE) -- lowRISC C.I.C., the open silicon ecosystem organisation, today announced the addition of formal ...